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Atomic Operations

Notes Lowlevel Asm C
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Gaurantees of Atomic Operations
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Atomic operations provide three main guarantees:

  1. Indivisibility: Atomic operations cannot be interrupted halfway through. So, it either completes fully or not at all.
  2. Visibility: Other cores can see the update consistently. No stale or torn reads.
  3. Ordering: Prevents reordering around the atomic operation, ensuring correct sequence of operations.

Normal C code is not atomic
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For example, consider the following C code:

ctr--;

On hardware this one line becomes:

load r1, [ctr]   ; Load current value of ctr into register r1
sub r1, r1, 1    ; Decrement the value in register r1
store [ctr], r1  ; Store the updated value back to memory

Between load and store another CPU can modify ctr, or a context switch can occur. This is why atomic operations are needed.

Atomic operations implementation
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The CPU locks exclusive access to a memory location or cache line while performing the operation. Example: in x86 there is a special atomic instruction

LOCK XADD [mem], reg

This:

  • Locks the cache line
  • Perform read + modify + write
  • Release lock

No other CPU can touch that memory during this window. Under the hood this is done using cache coherence protocols like MESI. This is also called a lock-based approach.

How does ARM do it?
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ARM does not lock the memory bus like x86. Instead it uses a pair of instructions:

LDXR r0, [addr]   ; Load + mark exclusive
STXR r1, r2, [addr] ; Store only if still exclusive

If another core touches the address:

  • STXR fails
  • Operation is retried

This is more efficient than locking the bus, allowing better concurrency. This is also called a reservation-based approach.